Evaluating the Impact of Process Variation on RRAMs

IEEE Latin American Test Symposium (LATS), pp. 1–6

Abstract

Over the last fifty years Complementary Metal Oxide Semiconductor (CMOS) technology has been scaled down, making the design of high-performance applications possible. However, there is a growing concern that device scaling will become infeasible below a certain feature size. In parallel, emerging applications present high demands regarding storage and computing capability, combined with challenging constraints. In this scenario, memristive devices have become promising candidates to replace or complement CMOS technology due to their CMOS manufacturing process compatibility, zero standby power consumption as well as high scalability and density. Despite these advantages, the implementation of high-density memories based on memristive devices poses some challenges related manufacturing process variation and consequently, to their reliability during lifetime. This paper investigates the impact of manufacturing process variation on Resistive Random Access Memories (RRAMs). In more detail, an evaluation of the RRAM's functionality when considering different levels of manufacturing process variation is performed. The obtained results show that different parameters can degrade the functionality of the RRAM cell as well as that there is a relation between the performed operating sequence and the tolerated percentage of variability. Finally, it is important to mention that understanding how process variation impacts the functionality of RRAM cells is considered essential to guarantee their reliability during lifetime, also allowing to optimize manufacturing processes.

Authors 7

1. E. Brum

   Pontifícia Universidade Católica do Rio Grande do Sul

   Affiliation as printed

   EASE, PUCRS,Brazil

   EASE, PUCRS, Brazil

2. Moritz Fieback

   Delft University of Technology

   Affiliation as printed

   Computer Engineering Laboratory, Delft University of Technology,The Netherlands

   Computer Engineering Laboratory, Delft University of Technology, The Netherlands

3. T. Copetti Aachen

   RWTH Aachen University

   Affiliation as printed

   IDS, RWTH Aachen University,Germany

   IDS, RWTH Aachen University, Germany

4. HE Jia-yi Aachen

   RWTH Aachen University

   Affiliation as printed

   IDS, RWTH Aachen University,Germany

   IDS, RWTH Aachen University, Germany

5. Said Hamdioui

   Delft University of Technology

   Affiliation as printed

   Computer Engineering Laboratory, Delft University of Technology,The Netherlands

   Computer Engineering Laboratory, Delft University of Technology, The Netherlands

6. Fabian Luis Vargas

   Pontifícia Universidade Católica do Rio Grande do Sul

   Affiliation as printed

   EASE, PUCRS,Brazil

   EASE, PUCRS, Brazil

7. L. M. Bolzani Poehls Aachen

   RWTH Aachen University

   Affiliation as printed

   IDS, RWTH Aachen University,Germany

   IDS, RWTH Aachen University, Germany