FPGA-based Acceleration of Lidar Point Cloud Processing and Detection on the Edge

IEEE Intelligent Vehicles Symposium, pp. 1–8

Abstract

Edge nodes such as Intelligent Transportation System Stations are becoming increasingly relevant in the context of automated driving as they provide connected vehicles with additional information to support their automated driving functions. However, the power budget for these edge nodes is limited and data has to be processed in real-time to be of use to automated driving functions. In this work, we present a system for processing raw lidar data in real-time on an FPGA, resulting in a significant reduction in power consumption compared to conventional hardware. Our approach leads to a 42.4% reduction in power consumption while maintaining the quality of the results. Processing two 128-layer surround-view lidar point clouds takes 522 ms per frame and an average power consumption of 39.3 W for the CPU and 34.5W for the FPGA. Our optimizations surpass the state-of-the-art by up to 193 times.

Authors 6

1. Cecilia Latotzke Aachen Chair of Integrated Digital Systems and Circuit Design (IDS)

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Chair of Integrated Digital Systems and Circuit Design,Aachen,Germany

   Chair of Integrated Digital Systems and Circuit Design, RWTH Aachen University, Aachen, Germany

2. Amarin Kloeker Aachen Institute for Automotive Engineering

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Institute for Automotive Engineering,Aachen,Germany

   Institute for Automotive Engineering, RWTH Aachen University, Aachen, Germany

3. Simon Schoening Aachen Chair of Integrated Digital Systems and Circuit Design (IDS)

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Chair of Integrated Digital Systems and Circuit Design,Aachen,Germany

   Chair of Integrated Digital Systems and Circuit Design, RWTH Aachen University, Aachen, Germany

4. Mazen Slimi Aachen Chair of Integrated Digital Systems and Circuit Design (IDS)

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Chair of Integrated Digital Systems and Circuit Design,Aachen,Germany

   Chair of Integrated Digital Systems and Circuit Design, RWTH Aachen University, Aachen, Germany

5. Lutz Eckstein Aachen Institute for Automotive Engineering

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Institute for Automotive Engineering,Aachen,Germany

   Institute for Automotive Engineering, RWTH Aachen University, Aachen, Germany

6. Tobias Gemmeke Aachen Chair of Integrated Digital Systems and Circuit Design (IDS)

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Chair of Integrated Digital Systems and Circuit Design,Aachen,Germany

   Chair of Integrated Digital Systems and Circuit Design, RWTH Aachen University, Aachen, Germany