Interface Engineering for Steep Slope Cryogenic MOSFETs

IEEE Electron Device Letters, vol. 43, pp. 2149–2152

Abstract

In this work, we study experimentally the impact of different gate dielectric stacks on the subthreshold behavior of cryogenic MOSFETs. While in room temperature devices, silicon nitride deteriorates the off-state of MOSFETs it turns out that at cryogenic temperatures an appropriately thin, grown silicon nitride layer in combination with a high-k gate dielectric counteracts the saturation of the inverse subthreshold slope and inflection phenomena. As a result, steep slope cryogenic MOSFETs with strongly improved subthreshold behavior are demonstrated.

Authors 7

1. Benjamin Richstein Aachen Institute of Semiconductor Electronics

   RWTH Aachen University

   Affiliation as printed

   Institute of Semiconductor Electronics, RWTH Aachen University, Aachen, Germany

2. Yi Han
   Affiliation as printed

   Peter Grünberg Institute (PGI 9), Jülich, Germany

3. Qing‐Tai Zhao
   Affiliation as printed

   Peter Grünberg Institute (PGI 9), Jülich, Germany

4. Lena Hellmich Aachen Institute of Semiconductor Electronics

   RWTH Aachen University

   Affiliation as printed

   Institute of Semiconductor Electronics, RWTH Aachen University, Aachen, Germany

5. Jan Klos Aachen JARA-FIT Institute for Quantum Information

   Jülich Aachen Research Alliance · RWTH Aachen University

   Affiliation as printed

   JARA-FIT Institute for Quantum Information, Forschungszentrum Jülich GmbH and RWTH Aachen University, Aachen, Germany

6. Lars R. Schreiber Aachen JARA-FIT Institute for Quantum Information

   Jülich Aachen Research Alliance · RWTH Aachen University

   Affiliation as printed

   JARA-FIT Institute for Quantum Information, Forschungszentrum Jülich GmbH and RWTH Aachen University, Aachen, Germany

7. Joachim Knoch Aachen Institute of Semiconductor Electronics

   RWTH Aachen University

   Affiliation as printed

   Institute of Semiconductor Electronics, RWTH Aachen University, Aachen, Germany