Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators

Abstract

The everlasting demand for higher computing power for deep neural networks (DNNs) drives the development of parallel computing architectures. 3D integration, in which chips are integrated and connected vertically, can further increase performance because it introduces another level of spatial parallelism. Therefore, we analyze dataflows, performance, area, power and temperature of such 3D-DNN-accelerators. Monolithic and TSV-based stacked 3D-ICs are compared against 2D-ICs. We identify workload properties and architectural parameters for efficient 3D-ICs and achieve up to 9. 14x speedup of 3Dvs.2D. We discuss area-performance trade-offs. We demonstrate applicability as the 3D-IC draws similar power as 2D-ICs and is not thermal limited.

Authors 7

1. Jan Moritz Joseph Aachen

   RWTH Aachen University · Georgia Institute of Technology

   Affiliation as printed

   Georgia Institute of Technology, Atlanta, GA

   RWTH Aachen University, Germany

   RWTH Aachen University (Germany)

2. Ananda Samajdar

   Georgia Institute of Technology

   Affiliation as printed

   Georgia Institute of Technology, Atlanta, GA

   , Georgia Institute of Technology, Atlanta, GA

3. Lingjun Zhu

   Georgia Institute of Technology

   Affiliation as printed

   Georgia Institute of Technology, Atlanta, GA

   , Georgia Institute of Technology, Atlanta, GA

4. Rainer Leupers Aachen

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University, Germany

   RWTH Aachen University (Germany)

5. Sung Kyu Lim

   Georgia Institute of Technology

   Affiliation as printed

   Georgia Institute of Technology, Atlanta, GA

   , Georgia Institute of Technology, Atlanta, GA

6. Thilo Pionteck

   Otto-von-Guericke-Universität Magdeburg

   Affiliation as printed

   Otto-von-Guericke-University Magdeburg, Germany

   Otto Von Guericke University,Magdeburg,Germany

7. Tushar Krishna

   Georgia Institute of Technology

   Affiliation as printed

   Georgia Institute of Technology, Atlanta, GA

   , Georgia Institute of Technology, Atlanta, GA