Ultra-low-power CMOS ring oscillator with minimum power consumption of 2.9 pW using low-voltage biasing technique

Open Engineering, vol. 14

Abstract

Abstract The need for low-power low-voltage circuit so lutions increases significantly with the rapid spread of wireless sensor network (WSN) and energy harvesting applications. The design of Complementary Metal-Oxide Semiconductor (CMOS) oscillators in sub-threshold region is challenged by the limits of the minimum start-up sup ply voltage, the power available from the harvester, die area, the demand of fully integrated CMOS circuits, and the additional auxiliary circuits that are needed to stabilize the frequency vs a supply voltage V DD. In this work, low-power CMOS oscillator with a simplified design is proposed in order to overcome the aforementioned obstacles. The circuit is designed using 2.5 µm 2-polySi 2-metal CMOS technology from IMB–CNM (CSIC) [1] with a threshold voltage of n-channel metal oxide semiconductor NMOS and p-channel metal oxide semiconductor PMOS transistors of 0.86 and −1.52 V, respectively. The suggested oscillator is capable to start up even in the deep sub-threshold region at V DD of 0.25 V. Accordingly, the minimum power consumption is 2.9 pW with an oscillation frequency of 2 Hz. The circuit can produce a P–P voltage of the oscillation signal equal to the supply voltage within a power supply range of 0.25–1.25 V.

Authors 1

1. Durgham Al-Shebanee corresponding Aachen Department of Electronics and Communications Engineering

   RWTH Aachen University · Al-Muthanna University

   Affiliation as printed

   Department of Electronics and Communications Engineering, Al-Muthanna University, Samawah, Iraq, Integrated Analog Circuits and RF Systems (researcher guest), RWTH Aachen University , Aachen, D-52062 , Germany