Automatic Generation of Structured Macros Using Standard Cells ‒ Application to CIM

IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 1–6

Abstract

Regularity can be exploited to efficiently describe, place and route logic blocks with a repetitive structure. We present a design flow to automatically generate regular, standard-cell based designs, which can be seamlessly integrated into a traditional digital flow in commercial EDA software. The generated arrays can be seamlessly integrated into a “sea of gates”. with no guard-rings or keep-out areas. The flow takes a description of a regular design as an input and generates netlist, placement, constraints, routing, initial parasitics estimates and timing information. We show that, in example designs, the run-time of EDA tooling is up to 2.5x faster, reduces the critical path by 47%, reduces the metal utilization by 45% and achieves a utilization of 93%.

Authors 4

1. Christian Lanius Aachen

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Aachen,Germany

   RWTH Aachen University, Aachen, Germany

2. Jie Lou Aachen

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Aachen,Germany

   RWTH Aachen University, Aachen, Germany

3. Johnson Loh Aachen

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Aachen,Germany

   RWTH Aachen University, Aachen, Germany

4. Tobias Gemmeke Aachen

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Aachen,Germany

   RWTH Aachen University, Aachen, Germany