4T Bitcell for Digital Compute-in-Memory

IEEE Nordic Circuits and Systems Conference (NorCAS), pp. 1–7

Abstract

Artificial neural networks (ANNs) are increasingly integrated into various aspects of modern life, thanks to significant advancements in their applications and performance in recent years. A major challenge in deploying these networks on lowpower edge devices is the substantial data movement required by traditional computing systems. Consequently, there is growing interest in digital Compute-in-Memory (CIM) solutions, which minimize data movement while preserving high accuracy and facilitating straightforward technology and voltage scaling. As area efficiency remains a challenge for digital CIM, development of novel bitcell designs is necessary. In this work, we present two standard cell-compliant static latches that can be placed alongside digital logic. The latches consist of 4 (6) transistors and require 73% (60%) less area compared to a standard latch. While the 6T latch features comparable noise margins to a standard design, the 4T latch achieves further area reduction at a smaller noise margin. We obviate the need for external reference voltages or multiple supply voltages by using a mixed threshold design. We show silicon measurement results for both latch implementations in a commercial 22nm technology throughout multiple voltages and temperatures and analyze their impact on neural network performance. Additionally, we present a system level analysis of an accelerator for Vector-Matrix-Multiplication (VMM) computation suggesting improvement in area efficiency of up to 74%, compared to a standard latch.

Authors 4

1. Florian Freye Aachen Chair of Integrated Digital Systems and Circuit Design (IDS)

   RWTH Aachen University

   Affiliation as printed

   Chair of Integrated Digital Systems and Circuit Design, RWTH Aachen,Aachen,Germany

2. Christian Lanius Aachen Chair of Integrated Digital Systems and Circuit Design (IDS)

   RWTH Aachen University

   Affiliation as printed

   Chair of Integrated Digital Systems and Circuit Design, RWTH Aachen,Aachen,Germany

3. Nils Mutert Aachen Chair of Integrated Digital Systems and Circuit Design (IDS)

   RWTH Aachen University

   Affiliation as printed

   Chair of Integrated Digital Systems and Circuit Design, RWTH Aachen,Aachen,Germany

4. Tobias Gemmeke Aachen Chair of Integrated Digital Systems and Circuit Design (IDS)

   RWTH Aachen University

   Affiliation as printed

   Chair of Integrated Digital Systems and Circuit Design, RWTH Aachen,Aachen,Germany