Compiling All-Digital-Embedded Content Addressable Memories on Chip for Edge Application

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, pp. 2560–2572

Abstract

A spectrum of emerging applications, including edge artificial intelligence, advocates the precompute-and-search scheme with embedded small-size content addressable memory (CAM) for its hardware efficiency instead of repetitive arithmetic operations. However, the integration of the CAM macros that are conventionally implemented with full custom analog circuits renders design-space exploration and optimization to be difficult at system level. As an alternative, a complete design flow for compiling ternary CAM on chip using foundry-supplied digital standard cells is introduced in this article. Based on the novel CAM architecture and logic design, we leverage guided placement and routing with mainstream EDA tools for exploiting the inherent structure regularity of CAM-cell arrays in the layout. An analytical model is also presented, which allows us for a systematic investigation on the energy reduction by adapting our design to various presearch structures. Validated on a postlayout$32{\times }64$ternary CAM in 28 nm, our parallel-matching scheme performs at 2.6 GHz with 0.42 fJ/bit/search, and the (8-bit) presearch scheme achieves 0.19 fJ/bit/search at 1.1 GHz, both under the 0.9-V supply voltage. In addition to flexibility for tradeoffs between the search throughput and energy, our all-digital CAM design enables voltage scaling aggressively down to 0.45 V with a minimum energy consumption of 0.06 fJ/bit/search at 50 MHz.

Authors 3

1. Xin Fan Aachen Institute of Integrated Digital Systems and Circuit Design

   RWTH Aachen University

   Affiliation as printed

   Institute of Integrated Digital Systems and Circuit Design, RWTH Aachen University, Aachen, Germany

2. Niklas Meyer Aachen Institute of Integrated Digital Systems and Circuit Design

   RWTH Aachen University

   Affiliation as printed

   Institute of Integrated Digital Systems and Circuit Design, RWTH Aachen University, Aachen, Germany

3. Tobias Gemmeke Aachen Institute of Integrated Digital Systems and Circuit Design

   RWTH Aachen University

   Affiliation as printed

   Institute of Integrated Digital Systems and Circuit Design, RWTH Aachen University, Aachen, Germany