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A secure hardware-software solution based on RISC-V, logic locking and microkernel2020 International Workshop on Software and Compilers for Embedded Systems (SCOPES) conference-paper Computer Science Security and Verification in Computing
Dominik Šišejković, Farhad Merchant, Lennart M. Reimann, Rainer Leupers, Massimiliano Giacometti, Sascha Kegreiß
21citations -
Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core2021 Design, Automation, and Test in Europe conference-paper Computer Science Security and Verification in Computing
Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Luca Benini, Gernot Heiser
16citations
3 results