Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core

Design, Automation, and Test in Europe, pp. 627–632

Abstract

Microarchitectural timing channels use variations in the timing of events, resulting from competition for limited hardware resources, to leak information in violation of the operating system's security policy. Such channels also exist on a simple in-order RISC-V core, as we demonstrate on the open-source RV64GC Ariane core. Time protection, recently proposed and implemented in the seL4 microkernel, aims to prevent timing channels, but depends on a controlled reset of microarchitectural state. Using Ariane, we show that software techniques for performing such a reset are insufficient and highly inefficient. We demonstrate that adding a single flush instruction is sufficient to close all five evaluated channels at negligible hardware costs, while requiring only minor modifications to the software stack.

Authors 5

1. Nils Wistoff Aachen ETH Zurich

   ETH Zurich · RWTH Aachen University

   Affiliation as printed

   ETH Zurich, At the time of this work also affiliated with RWTH Aachen and HENSOLDT Cyber GmbH, Zurich, Switzerland

2. Moritz Schneider Aachen ETH Zurich

   ETH Zurich · RWTH Aachen University

   Affiliation as printed

   ETH Zurich, At the time of this work also affiliated with RWTH Aachen and HENSOLDT Cyber GmbH, Zurich, Switzerland

3. Frank K. Gürkaynak Aachen ETH Zurich

   ETH Zurich · RWTH Aachen University

   Affiliation as printed

   ETH Zurich, At the time of this work also affiliated with RWTH Aachen and HENSOLDT Cyber GmbH, Zurich, Switzerland

4. Luca Benini

   ETH Zurich · University of Bologna

   Affiliation as printed

   ETH Zurich and University of Bologna, Zurich, Switzerland

5. Gernot Heiser

   Commonwealth Scientific and Industrial Research Organisation · UNSW Sydney · Data61

   Affiliation as printed

   UNSW Sydney and Data61 CSIRO, Sydney, Australia