Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware

Proceedings - ACM IEEE Design Automation Conference, pp. 1–6

Abstract

Logic-in-memory (LIM) describes the execution of logic gates within memristive crossbar structures, promising to improve performance and energy efficiency. Utilizing only binary values, LIM particularly excels in accelerating binary neural networks, shifting it in the focus of edge applications. Considering its potential, the impact of faults on BNNs accelerated with LIM still lacks investigation. In this paper, we propose faulty logic-in-memory (FLIM), a fault injection platform capable of executing full-fledged BNNs on LIM while injecting in-field faults. The results show that FLIM runs a single MNIST picture 66754× faster than the state of the art by offering a fine-grained fault injection methodology.

Authors 7

1. Felix Staudigl Aachen Institute for Communication Technologies and Embedded Systems

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Institute for Communication Technologies and Embedded Systems,Germany

   Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Germany

2. Thorben Fetz Aachen Institute for Communication Technologies and Embedded Systems

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Institute for Communication Technologies and Embedded Systems,Germany

   Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Germany

3. Rebecca Pelke Aachen Institute for Communication Technologies and Embedded Systems

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Institute for Communication Technologies and Embedded Systems,Germany

   Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Germany

4. Dominik Šišejković Aachen Institute for Communication Technologies and Embedded Systems

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Institute for Communication Technologies and Embedded Systems,Germany

   Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Germany

5. Jan Moritz Joseph Aachen Institute for Communication Technologies and Embedded Systems

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Institute for Communication Technologies and Embedded Systems,Germany

   Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Germany

6. Leticia Bolzani Pöhls Aachen Chair of Integrated Digital Systems and Circuit Design (IDS)

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Chair of Integrated Digital Systems and Circuit Design,Germany

   Chair of Integrated Digital Systems and Circuit Design, RWTH Aachen University, Germany

7. Rainer Leupers Aachen Institute for Communication Technologies and Embedded Systems

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Institute for Communication Technologies and Embedded Systems,Germany

   Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Germany