Reliability aspects of binary vector-matrix-multiplications using ReRAM devices

Neuromorphic Computing and Engineering, vol. 2, pp. 034001

Abstract

Abstract Computation-in-memory using memristive devices is a promising approach to overcome the performance limitations of conventional computing architectures introduced by the von Neumann bottleneck which are also known as memory wall and power wall. It has been shown that accelerators based on memristive devices can deliver higher energy efficiencies and data throughputs when compared with conventional architectures. In the vast multitude of memristive devices, bipolar resistive switches based on the valence change mechanism (VCM) are particularly interesting due to their low power operation, non-volatility, high integration density and their CMOS compatibility. While a wide range of possible applications is considered, many of them such as artificial neural networks heavily rely on vector-matrix-multiplications (VMMs) as a mathematical operation. These VMMs are made up of large numbers of multiplication and accumulation (MAC) operations. The MAC operation can be realised using memristive devices in an analog fashion using Ohm’s law and Kirchhoff’s law. However, VCM devices exhibit a range of non-idealities, affecting the VMM performance, which in turn impacts the overall accuracy of the application. Those non-idealities can be classified into time-independent (programming variability) and time-dependent (read disturb and read noise). Additionally, peripheral circuits such as analog to digital converters can introduce errors during the digitalization. In this work, we experimentally and theoretically investigate the impact of device- and circuit-level effects on the VMM in a VCM crossbars. Our analysis shows that the variability of the low resistive state plays a key role and that reading in the RESET direction should be favored to reading in the SET direction.

Authors 10

1. Christopher Bengel corresponding Aachen

   Jülich Aachen Research Alliance · RWTH Aachen University

   Affiliation as printed

   Institute of Materials in Electrical Engineering and Information Technology II and Jülich Aachen Research Alliance (JARA)-Fit, Rheinisch-Westfälische Technische Hochschule (RWTH) Aachen University, Aachen, Germany

   RWTH Aachen IWE 2, Sommerfeldstraße 18/24, Aachen, 52074, GERMANY

2. Johannes Mohr corresponding Aachen

   Jülich Aachen Research Alliance · RWTH Aachen University

   Affiliation as printed

   Institute of Materials in Electrical Engineering and Information Technology II and Jülich Aachen Research Alliance (JARA)-Fit, Rheinisch-Westfälische Technische Hochschule (RWTH) Aachen University, Aachen, Germany

   RWTH Aachen IWE 2, Sommerfeldstraße 18/24, Aachen, 52074, GERMANY

3. Stefan Wiefels corresponding

   Forschungszentrum Jülich · Jülich Aachen Research Alliance

   Affiliation as printed

   Peter Grünberg Institute PGI 7, Forschungszentrum Jülich GmbH and JARA-FIT, Jülich, Germany

   Forschungszentrum Jülich GmbH, Peter Grünberg Institut (PGI-7), Julich, Nordrhein-Westfalen, 52428, GERMANY

4. Abhairaj Singh corresponding

   Delft University of Technology

   Affiliation as printed

   Computer Engineering Department, Delft University of Technology, 2628 CD Delft, The Netherlands

   Computer Engineering Lab, TU Delft, Mekelweg 4, Delft, Zuid-Holland, 2600 AA, NETHERLANDS

5. Anteneh Gebregiorgis corresponding

   Delft University of Technology

   Affiliation as printed

   Computer Engineering Department, Delft University of Technology, 2628 CD Delft, The Netherlands

   Computer Engineering Lab, TU Delft, Mekelweg 4, Delft, Zuid-Holland, 2600 AA, NETHERLANDS

6. Rajendra Bishnoi corresponding

   Delft University of Technology

   Affiliation as printed

   Computer Engineering Department, Delft University of Technology, 2628 CD Delft, The Netherlands

   Computer Engineering Lab, TU Delft, Mekelweg 4, Delft, Zuid-Holland, 2600 AA, NETHERLANDS

7. Said Hamdioui corresponding

   Delft University of Technology

   Affiliation as printed

   Computer Engineering Department, Delft University of Technology, 2628 CD Delft, The Netherlands

   Coputer Engineering Lab, TU Delft, Mekelweg 4, Delft, Zuid-Holland, 2600 AA, NETHERLANDS

8. Rainer M. Waser corresponding Aachen

   Forschungszentrum Jülich · Jülich Aachen Research Alliance · RWTH Aachen University

   Affiliation as printed

   Institute of Materials in Electrical Engineering and Information Technology II and Jülich Aachen Research Alliance (JARA)-Fit, Rheinisch-Westfälische Technische Hochschule (RWTH) Aachen University, Aachen, Germany

   Peter Grünberg Institute PGI 10, Forschungszentrum Jülich GmbH and JARA-FIT, Jülich, Germany

   Peter Grünberg Institute PGI 7, Forschungszentrum Jülich GmbH and JARA-FIT, Jülich, Germany

   Forschungszentrum Jülich GmbH, Peter Grünberg Institut (PGI-7), Peter Grünberg Institut (PGI-10), Julich, Nordrhein-Westfalen, 52428, GERMANY

9. Dirk J. Wouters corresponding Aachen

   Jülich Aachen Research Alliance · RWTH Aachen University

   Affiliation as printed

   Institute of Materials in Electrical Engineering and Information Technology II and Jülich Aachen Research Alliance (JARA)-Fit, Rheinisch-Westfälische Technische Hochschule (RWTH) Aachen University, Aachen, Germany

   RWTH Aachen IWE 2, Sommerfeldstraße 18/24, Aachen, 52074, GERMANY

10. Stephan Menzel corresponding

    Forschungszentrum Jülich · Jülich Aachen Research Alliance

    Affiliation as printed

    Peter Grünberg Institute PGI 7, Forschungszentrum Jülich GmbH and JARA-FIT, Jülich, Germany

    Forschungszentrum Jülich GmbH, Peter Grünberg Institut (PGI-7), Julich, Nordrhein-Westfalen, 52428, GERMANY