January 01, 2016 conference-paper Improving SRAM Test Quality by Leveraging Self-timed Circuits Design, Automation, and Test in Europe DOI: 10.3850/9783981537079_0840 OpenAlex Authors 0 Author list not loaded yet. Cited by 3 stored of 6 Search Sort Most cited Newest Oldest Patent citations Title Any typearticle review book-chapter conference-paper preprint dissertation book dataset other Any fieldAgricultural and Biological Sciences Arts and Humanities Biochemistry, Genetics and Molecular Biology Business, Management and Accounting Chemical Engineering Chemistry Computer Science Decision Sciences Dentistry Earth and Planetary Sciences Economics, Econometrics and Finance Energy Engineering Environmental Science Health Professions Immunology and Microbiology Materials Science Mathematics Medicine Neuroscience Nursing Pharmacology, Toxicology and Pharmaceutics Physics and Astronomy Psychology Social Sciences Veterinary Open access Hierarchical Memory Diagnosis 2022 Proceedings/Proceedings - European Test Workshop conference-paper Computer Science VLSI and Analog Circuit Testing Open access 0 citations Detecting Random Read Faults to Reduce Test Escapes in FinFET SRAMs 2021 Proceedings/Proceedings - European Test Workshop conference-paper Computer Science VLSI and Analog Circuit Testing Open access 6 citations Hard-to-Detect Fault Analysis in FinFET SRAMs 2021 IEEE Transactions on Very Large Scale Integration (VLSI) Systems article Computer Science VLSI and Analog Circuit Testing Open access 15 citations 3 results References 0