A (145, 128) DEC-TED BCH Decoder with Composite Field and Redundant Arithmetic

IEEE Nordic Circuits and Systems Conference (NorCAS), pp. 1–7

Abstract

In this paper, a (145, 128) double error correcting and triple error detecting (DEC-TED) BCH decoder utilizing composite field representation and redundant arithmetic is presented. We explore the effect of the field representation by comparing area efficiency and energy efficiency for$\text{GF}\left(2^{8}\right)$,$\text{GF}\left(\left(2^{4}\right)^{2}\right)$and$\text{GF}\left(\left(\left(2^{2}\right)^{2}\right)^{2}\right)$implementations and also$\text{GF}\left(\left(2^{4}\right)^{2}\right)$with redundantly represented basis (RRB) for the base-field. Both Chien search and analytical solving of the error locator polynomial (ELP) are explored. Post layout simulations in a$\mathbf{2 2 ~ n m ~ f d S O I ~ t e c h n o l o g y ~ s h o w ~ t h a t ~ t h e ~ a n a l y t i c a l ~ s o l u t i o n ~ o f ~ E L P ~}$using$\operatorname{GF}\left(\left(2^{4}\right)^{2}\right)$with redundantly represented basis (RRB) for the base-field dominates the area efficiency versus energy efficiency Pareto front.

Authors 3

1. Hossein Hashemi Shadmehri Aachen Chair of Integrated Digital Systems and Circuit Design (IDS)

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Chair of Integrated Digital Systems and Circuit Design,Aachen,Germany

2. Christian Lanius Aachen Chair of Integrated Digital Systems and Circuit Design (IDS)

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Chair of Integrated Digital Systems and Circuit Design,Aachen,Germany

3. Tobias Gemmeke Aachen Chair of Integrated Digital Systems and Circuit Design (IDS)

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Chair of Integrated Digital Systems and Circuit Design,Aachen,Germany