Exploring Hardware-Efficient Architectures of Golomb–Rice Decoder for TinyML Applications

Journal of Circuits Systems and Computers, vol. 34

Abstract

Deep Neural Networks (DNNs) have revolutionized Artificial Intelligence (AI) applications by tackling real-world problems. Yet, their deployment on Internet of Things (IoT) edge devices remains challenging due to limited resources. The energy-intensive process of accessing millions of parameters during DNN inference has become a significant bottleneck. While weight compression offers a potential solution, existing hardware decompression units struggle to maintain power, area, energy efficiency. This research introduces two innovative decoders: an Interleaved-memory-based Parallel (ImbP) GR decoder and a scalable Tree-Unary-based Parallel (TubP) GR decoder. By integrating these decoders with an industrial-strength Neural Network (NN) accelerator, their performance was evaluated using three TinyML benchmarks. Comparative analysis revealed that the TuP GR decoder outperforms the ImP GR decoder regarding performance metrics and hardware efficiency. The scalable TubP GR decoder achieves remarkable efficiency, offering 4-weight and 8-weight decoding capabilities that consume 0.43[Formula: see text]mW and 0.79[Formula: see text]mW, respectively, while delivering impressive throughput rates of 888[Formula: see text]MBps and 1.3[Formula: see text]GBps.

Authors 3

1. Mounika Vaddeboina

   Infineon Technologies (Germany)

   Affiliation as printed

   Infineon Technologies AG — Technische Universität München, Am Campeon 1-15, München 85579, Germany

2. Alper Yilmazer Aachen

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University, Templergraben 55, Aachen 52062, Germany

3. Wolfgang Ecker

   Infineon Technologies (Germany)

   Affiliation as printed

   Infineon Technologies AG — Technische Universität München, Am Campeon 1-15, München 85579, Germany