Rapid RISC-V Floating Point Vector Simulation

Abstract

Instruction Set Simulators (ISSs) are important tools for software engineers that develop cross-system applications.To facilitate seamless interaction between user and ISS, achieving a high simulation performance is key.One of the most challenging simulation aspects is the modeling of Floating Point (FP) vector instructions.Differences among Instruction Set Architectures (ISAs), as well as side effects like FP exception flags, require a significant modeling effort, leading to a reduced simulation performance.Moreover, even state-of-the-art simulators, such as QEMU, use scalar instructions to model vector instructions, which even further hampers the simulator's performance.In this paper, we not only propose new methods for the fast simulation of FP vector instructions, we also show how vector instructions of the host system can be leveraged.To demonstrate the practical benefits of our method, we conducted a RISC-V-on-x64 case study.Compared to QEMU, our approach achieves a speedup of 3.5× for individual instructions.As part of a Virtual Platform (VP) executing vector benchmarks, speedups of up to 24.6% can be attained.

Authors 4

1. Niko Zurstraßen Aachen

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University, Aachen, Germany

2. Nils Bosbach Aachen

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University, Aachen, Germany

3. Lukas Jünger
   Affiliation as printed

   MachineWare GmbH, Aachen, Germany

4. Rainer Leupers Aachen

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University, Aachen, Germany