Loss-Compensated Cascaded Multistage Distributed Power Amplifier in 65nm CMOS Technology
IEEE Access, vol. 12, pp. 98917–98927
Abstract
This work presents the analysis, design, and implementation of a fully integrated loss-compensated cascaded multistage distributed amplifier (LC-CMSDA) in$65nm$CMOS technology. The proposed LC-CMSDA consists of three distributed stages in cascade configuration. The input stage utilizes three gain-cells in a distributive topology and offers 10 dB of gain. The second stage deploys two-sections while the output stage has three gain-sections in a distributive configuration. The interstage artificial lines are tapered towards large gain and high output power. Interstage inductive peaking in the gain-cell and high frequency loss-compensation at the gate of the cascode, extend the bandwidth. The RF chokes of all three stages have been realized on-chip that leads to a fully integrated design. Small-signal measurement results demonstrate measured peak gain of 21.5 dB and minimum gain of 9 dB through 50GHz of bandwith, resulting into a 146 GHz gain-bandwidth product. Large-signal characterization show peak saturated output power of 14.93 dBm with a peak drain efficiency of 8.95%. The third-order intercept point is better than 15 dBm. The proposed LC-CMSDA occupies only an area of$1.33~mm^{2}$.
Authors 4
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Affiliation as printed
Department of Electronics Engineering, University of Chakwal, Chakwal, Pakistan
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Pak-Austria Fachhochschule: Institute of Applied Sciences and Technology
Affiliation as printed
Department of Electrical and Computer Engineering, Pak-Austria Fachhochschule: Institute of Applied Sciences and Technology, Haripur, Khyber Pakhtunkhwa, Pakistan
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Affiliation as printed
Department of Physics, University of Chakwal, Chakwal, Pakistan
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Affiliation as printed
Chair of High Frequency Electronics, RWTH Aachen University, Aachen, Germany
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