AIfES: A Next-Generation Edge AI Framework

IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 46, pp. 4519–4533

Abstract

Edge Artificial Intelligence (AI) relies on the integration of Machine Learning (ML) into even the smallest embedded devices, thus enabling local intelligence in real-world applications, e.g. for image or speech processing. Traditional Edge AI frameworks lack important aspects required to keep up with recent and upcoming ML innovations. These aspects include low flexibility concerning the target hardware and limited support for custom hardware accelerator integration. Artificial Intelligence for Embedded Systems Framework (AIfES) has the goal to overcome these challenges faced by traditional edge AI frameworks. In this paper, we give a detailed overview of the architecture of AIfES and the applied design principles. Finally, we compare AIfES with TensorFlow Lite for Microcontrollers (TFLM) on an ARM Cortex-M4-based System-on-Chip (SoC) using fully connected neural networks (FCNNs) and convolutional neural networks (CNNs). AIfES outperforms TFLM in both execution time and memory consumption for the FCNNs. Additionally, using AIfES reduces memory consumption by up to 54% when using CNNs. Furthermore, we show the performance of AIfES during the training of FCNN as well as CNN and demonstrate the feasibility of training a CNN on a resource-constrained device with a memory usage of slightly more than 100 kB of RAM.

Authors 6

1. Lars Wulfert

   Fraunhofer Institute for Microelectronic Circuits and Systems

   Affiliation as printed

   Fraunhofer Institute for Microelectronic Circuits and Systems, Dusiburg, Germany

   Fraunhofer Institute for Microelectronic Circuits and Systems, North rhine westphalia, Ger, Dusiburg, Germany

2. Lukas Krupp

   Fraunhofer Institute for Microelectronic Circuits and Systems

   Affiliation as printed

   Fraunhofer Institute for Microelectronic Circuits and Systems, Dusiburg, Germany

   Fraunhofer Institute for Microelectronic Circuits and Systems, North rhine westphalia, Ger, Dusiburg, Germany

3. Justus Viga Aachen

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University, Aachen, Germany

   RWTH Aachen University, North rhine westphalia, Ger, Aachen, Germany

4. Christian Wiede

   Fraunhofer Institute for Microelectronic Circuits and Systems

   Affiliation as printed

   Fraunhofer Institute for Microelectronic Circuits and Systems, Dusiburg, Germany

   Fraunhofer Institute for Microelectronic Circuits and Systems, North rhine westphalia, Ger, Dusiburg, Germany

5. Pierre Gembaczka

   Fraunhofer Institute for Microelectronic Circuits and Systems

   Affiliation as printed

   Fraunhofer Institute for Microelectronic Circuits and Systems, Dusiburg, Germany

   Fraunhofer Institute for Microelectronic Circuits and Systems, North rhine westphalia, Ger, Dusiburg, Germany

6. Anton Grabmaier

   Fraunhofer Institute for Microelectronic Circuits and Systems

   Affiliation as printed

   Fraunhofer Institute for Microelectronic Circuits and Systems, Dusiburg, Germany

   Fraunhofer Institute for Microelectronic Circuits and Systems, North rhine westphalia, Ger, Dusiburg, Germany