Qubit Bias using a CMOS DAC at mK Temperatures

IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 1–4

Abstract

Scaling up a quantum processor to tackle real-world problems requires qubit numbers in the millions. Scalable semiconductor-based architectures have been proposed, many of them relying on integrated control instead of room-temperature electronics. However, it has not yet been shown that this can be achieved. For developing a high-density, low-cost wiring solution, it is highly advantageous for the electronics to be placed at the same temperature as the qubit chip. Therefore, tight integration of the qubit chip with ultra low power complemen-tary metal-oxide-semiconductor (CMOS) electronics presents a promising route. We demonstrate DC biasing qubit electrodes using a custom-designed 65nm CMOS capacitive digital-to-analog converter (DAC) operating on the mixing chamber of a dilution refrigerator below 45 mK. Our chip features a complete proof of principle solution including interface, DAC memory and logic, the capacitive DAC, and sample-and-hold structures to provide voltages for multiple qubit gates. The bias- DAC is combined with the qubit using a silicon interposer chip, enabling flexible routing and tight integration. Voltage stability, noise performance, and temperature are benchmarked using the qubit chip. Our results indicate that qubit bias at cryogenic temperatures with a power consumption of 4 n W /ch is feasible with this approach. They validate the potential of very low power qubit biasing using highly integrated circuits whose connectivity requirements do not increase with the number of qubits.

Authors 7

1. René Otten Aachen JARA-Institute for Quantum Information

   Jülich Aachen Research Alliance · RWTH Aachen University

   Affiliation as printed

   JARA Institute for Quantum Information, RWTH Aachen University and Forschungszentrum Jülich GmbH,Aachen,Germany

2. Lea Schreckenberg

   Forschungszentrum Jülich

   Affiliation as printed

   Central Institute of Engineering,Electronics and Analytics, Electronic Systems (ZEA-2) Forschungszentrum Jülich GmbH,Jülich,Germany

3. Patrick Vliex

   Forschungszentrum Jülich

   Affiliation as printed

   Central Institute of Engineering,Electronics and Analytics, Electronic Systems (ZEA-2) Forschungszentrum Jülich GmbH,Jülich,Germany

4. Julian Ritzmann

   Ruhr University Bochum

   Affiliation as printed

   Ruhr-Universitat Bochum,Lehrstuhl für Angewandte Festkorperphysik,Bochum,Germany

5. Arne Ludwig

   Ruhr University Bochum

   Affiliation as printed

   Ruhr-Universitat Bochum,Lehrstuhl für Angewandte Festkorperphysik,Bochum,Germany

6. Andreas Dirk Wieck

   Ruhr University Bochum

   Affiliation as printed

   Ruhr-Universitat Bochum,Lehrstuhl für Angewandte Festkorperphysik,Bochum,Germany

7. Hendrik Bluhm Aachen JARA-Institute for Quantum Information

   Jülich Aachen Research Alliance · RWTH Aachen University

   Affiliation as printed

   JARA Institute for Quantum Information, RWTH Aachen University and Forschungszentrum Jülich GmbH,Aachen,Germany