Designing ML-resilient locking at register-transfer level

Proceedings - ACM IEEE Design Automation Conference, pp. 769–774

Abstract

Various logic-locking schemes have been proposed to protect hardware from intellectual property piracy and malicious design modifications. Since traditional locking techniques are applied on the gate-level netlist after logic synthesis, they have no semantic knowledge of the design function. Data-driven, machine-learning (ML) attacks can uncover the design flaws within gate-level locking. Recent proposals on register-transfer level (RTL) locking have access to semantic hardware information. We investigate the resilience of ASSURE, a state-of-the-art RTL locking method, against ML attacks. We used the lessons learned to derive two ML-resilient RTL locking schemes built to reinforce ASSURE locking. We developed ML-driven security metrics to evaluate the schemes against an RTL adaptation of the state-of-the-art, ML-based SnapShot attack.

Authors 6

1. Dominik Šišejković Aachen

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University, Germany

2. Luca Collini

   New York University

   Affiliation as printed

   New York University

3. Benjamin Tan

   University of Calgary

   Affiliation as printed

   University of Calgary, Canada

4. Christian Pilato

   Politecnico di Milano

   Affiliation as printed

   Politecnico di Milano, Italy

5. Ramesh Karri

   New York University

   Affiliation as printed

   New York University

6. Rainer Leupers Aachen

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University, Germany