Defect tolerant in-memory analog computing with CMOS-integrated nanoscale crossbars: Invited

IEEE International Conference on Electronics, Circuits and Systems (ICECS), vol. 453, pp. 1–4

Abstract

There is an increasing amount of effort to build a fast, energy-efficient, large-scale, and, most importantly, reliable memristor crossbar system for in-memory analog computing. Silicon transistors are used as selectors and on-chip control peripheral circuits to fully unleash the power of the emerging devices. Still, unexpected computing errors occur because of non-ideal device performance. Herein, we review two promising solutions. The first one is the in-situ training of memristor neural networks to self-adapt various defects, and the second one is an analog error-correcting code that detects and corrects unexpected errors with minimum hardware overhead.

Authors 4

1. Mingrui Jiang

   University of Hong Kong

   Affiliation as printed

   Department of EEE, The University of Hong Kong, Hong Kong, SAR China

2. Ruibin Mao

   University of Hong Kong

   Affiliation as printed

   Department of EEE, The University of Hong Kong, Hong Kong, SAR China

3. John Paul Strachan Aachen

   Forschungszentrum Jülich · RWTH Aachen University

   Affiliation as printed

   Peter Grünberg Institut (PGI-14), Forschungszentrum Jülich GmbH, Jülich, Germany

   RWTH Aachen University, Aachen, Germany

4. Can Li

   University of Hong Kong

   Affiliation as printed

   Department of EEE, The University of Hong Kong, Hong Kong, SAR China