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All-Digital Delay-Locked Loop-based Frequency Multiplier Operating from 4.0GHz to 5.6GHz

International Conference on Electrical, Communication, and Computer Engineering (ICECCE), pp. 1–5

Abstract

In this paper, a high speed, small area and highly reliable frequency multiplier based on an all-digital delay-locked loop (ADDLL) implemented with TSMC 65nm CMOS technology is proposed. A comparison between the two multiplication factors of 40 and 20 for the proposed edge combiner is also presented. The proposed ADDLL uses a 5-bit up/down counter to control the digital delay line. The delay difference is achieved with 3ps in the proposed design based on a post layout simulation. The simulated operating frequency range is between 100MHz to 140MHz for a multiplication factor of 40; and 220MHz to 240MHz for the multiplication factor of 20. The output signal in a frequency range from 4.0GHz to 5.6GHz can be generated. Based on the simulation results peak-to-peak jitter is 28.2ps and 22.2ps for the output signal with a frequency of 4.88GHz and 4.5GHz while the DLL operates at 122MHz and 225MHz, respectively.

Authors 5

  1. RWTH Aachen University

    Affiliation as printed

    Chair of High Frequency Electronics, RWTH Aachen University, Aachen, Germany

  2. RWTH Aachen University

    Affiliation as printed

    Chair of High Frequency Electronics, RWTH Aachen University, Aachen, Germany

  3. RWTH Aachen University

    Affiliation as printed

    Chair of High Frequency Electronics, RWTH Aachen University, Aachen, Germany

  4. King Mongkut's University of Technology North Bangkok

    Affiliation as printed

    The Sirindhorn International TGGS, King Mongkut's U. of Tech. North, Bangkok, Thailand

  5. RWTH Aachen University

    Affiliation as printed

    Chair of High Frequency Electronics, RWTH Aachen University, Aachen, Germany

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References 11

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