March 01, 2005 article A wide-range and fast-locking all-digital cycle-controlled delay-locked loop IEEE Journal of Solid-State Circuits DOI: 10.1109/jssc.2005.843596 OpenAlex Authors 0 Author list not loaded yet. Cited by 1 stored of 79 Search Sort Most cited Newest Oldest Patent citations Title Any typearticle review book-chapter conference-paper preprint dissertation book dataset other Any fieldAgricultural and Biological Sciences Arts and Humanities Biochemistry, Genetics and Molecular Biology Business, Management and Accounting Chemical Engineering Chemistry Computer Science Decision Sciences Dentistry Earth and Planetary Sciences Economics, Econometrics and Finance Energy Engineering Environmental Science Health Professions Immunology and Microbiology Materials Science Mathematics Medicine Neuroscience Nursing Pharmacology, Toxicology and Pharmaceutics Physics and Astronomy Psychology Social Sciences Veterinary Open access All-Digital Delay-Locked Loop-based Frequency Multiplier Operating from 4.0GHz to 5.6GHz 2020 International Conference on Electrical, Communication, and Computer Engineering (ICECCE) conference-paper Engineering Advancements in PLL and VCO Technologies 5 citations 1 result References 0