February 01, 2018 conference-paper A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference DOI: 10.1109/isscc.2018.8310401 OpenAlex Authors 0 Author list not loaded yet. Cited by 2 stored of 252 Search Sort Most cited Newest Oldest Patent citations Title Any typearticle review book-chapter conference-paper preprint dissertation book dataset other Any fieldAgricultural and Biological Sciences Arts and Humanities Biochemistry, Genetics and Molecular Biology Business, Management and Accounting Chemical Engineering Chemistry Computer Science Decision Sciences Dentistry Earth and Planetary Sciences Economics, Econometrics and Finance Energy Engineering Environmental Science Health Professions Immunology and Microbiology Materials Science Mathematics Medicine Neuroscience Nursing Pharmacology, Toxicology and Pharmaceutics Physics and Astronomy Psychology Social Sciences Veterinary Open access An Energy Efficient All-Digital Time-Domain Compute-in-Memory Macro Optimized for Binary Neural Networks 2023 IEEE Transactions on Circuits and Systems I Regular Papers article Engineering Advanced Memory and Neural Computing 17 citations All-Digital Time-Domain Compute-in-Memory Engine for Binary Neural Networks With 1.05 POPS/W Energy Efficiency 2022 Proceedings of ESSCIRC conference-paper Engineering Advanced Memory and Neural Computing 19 citations 2 results References 0