June 13, 2010 conference-paper Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs DOI: 10.1145/1811100.1811108 OpenAlex Authors 0 Author list not loaded yet. Cited by 2 stored of 55 Search Sort Most cited Newest Oldest Patent citations Title Any typearticle review book-chapter conference-paper preprint dissertation book dataset other Any fieldAgricultural and Biological Sciences Arts and Humanities Biochemistry, Genetics and Molecular Biology Business, Management and Accounting Chemical Engineering Chemistry Computer Science Decision Sciences Dentistry Earth and Planetary Sciences Economics, Econometrics and Finance Energy Engineering Environmental Science Health Professions Immunology and Microbiology Materials Science Mathematics Medicine Neuroscience Nursing Pharmacology, Toxicology and Pharmaceutics Physics and Astronomy Psychology Social Sciences Veterinary Open access High-Level Formulas for the 3D-Interconnect Power Consumption and Performance 2022 Springer eBooks book-chapter Engineering 3D IC and TSV technologies 0 citations Low-Power Technique for 3D Interconnects 2022 Springer eBooks book-chapter Engineering 3D IC and TSV technologies 0 citations 2 results References 0