DEVICE AND METHOD FOR OPERATING A SEMICONDUCTOR SPIN QUBIT QUANTUM COMPUTER
Abstract
A method, using a microprocessor, of operating a quantum chip (10), wherein the quantum chip comprises a semiconductor heterostructure (12) and a plurality of gate electrodes (50) arranged on the semiconductor heterostructure (12) to provide a plurality of shuttling lanes (16) for moving a plurality of qubits along a plurality of paths (45); the plurality of gate electrodes (50) are further arranged to form a plurality of manipulation zones (20) and a plurality of T-junctions (18), any one of the plurality of manipulation zones (20) comprising an interface (25), at which two of the plurality of shuttling lanes (16) meet one another, and any one of the plurality of T-junctions (18) comprising a junction (28), at which one of the plurality of shuttling lanes (16) joins another one of the plurality of shuttling lanes (16); the method comprising the steps of calibrating voltage parameters pertaining to voltages to be applied to the plurality of gate electrodes (50), one of the parameters pertaining to one of the plurality of gate electrodes (50); selecting a path (45s) along selected ones (16-1, 16-2,..., 16- n) of the plurality of shuttling lanes (16) between a position (S) of a qubit and a selected manipulation zone (20); determining, based on the voltage parameters, for any one of the selected ones (16-1, 16-2,..., 16-n) of the plurality of shuttling lanes (16), at least one shuttling voltage time course to be applied to the associated subset (50i) of the plurality of gate electrodes (50), to move the qubit from the current position to the selected manipulation zone (20); moving the qubit along the selected ones (16-1, 16-2,..., 16-n) of the plurality of shuttling lanes (16) from the current position (S) to the selected manipulation zone (20), by applying the shuttling voltage time courses to subsets (50-1, 50-2,..., 50-n) of the plurality of gate electrodes (50), associated with the selected ones (16-1, 16-2,..., 16-n) of the plurality of shuttling lanes (16); determining, based on the voltage parameters, for the selected manipulation zone (20), a manipulation voltage time course to be applied to the associated subsets (50-n, 50-s) of the plurality of gate electrodes (50), to manipulate the qubit; and manipulating the qubit at the selected manipulation zone (20) by applying at least one manipulation voltage time course to the subsets (50-n, 50-s) of the plurality of gate electrodes (50), associated with the selected manipulation zone (20).
Inventors 3
- Jan Klos Aachen author as filed: Klos, Jan
- Matthias Künne Aachen author as filed: Künne, Matthias
- Pascal Cerfontaine Aachen author as filed: Cerfontaine, Pascal
Inventors are linked to an Aachen author when surname and first name match exactly one author.
Applicants
- FORSCHUNGSZENTRUM JÜLICH GMBH
- RHEINISCH-WESTFÄLISCHE TECHNISCHE HOCHSCHULE (RWTH) AACHEN RWTH Aachen University
Cited papers 1 in the database
Non-patent literature as cited (5)
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