QUANTUM COMPUTER DESIGN
Abstract
Method for designing a quantum computing element (1) for performing a quantum algorithm, wherein the quantum computing element (1) is configured to be operated with a plurality of spin qubits (9) and has a plurality of shuttling lanes (4) with a plurality of building blocks (13), and wherein the method comprises: a) providing a respective mathematical model for each of the building blocks (13), b) providing an initial design of the quantum computing element (1), c) creating a mathematical model of the initial design by combining the mathematical models of the building blocks (13) according to the initial design, d) obtaining an improved design of the quantum computing element (1) using the mathematical model of the initial design created in step c) and taking account of the quantum algorithm to be performed with the quantum computing element (1).
Inventors 2
- Matthias Künne Aachen author as filed: Künne, Matthias
- Pascal Cerfontaine Aachen author as filed: Cerfontaine, Pascal
Inventors are linked to an Aachen author when surname and first name match exactly one author.
Applicants
- RHEINISCH-WESTFÄLISCHE TECHNISCHE HOCHSCHULE (RWTH) AACHEN RWTH Aachen University
Cited papers 0 in the database
Non-patent literature as cited (3)
- - MUHAMMAD AHSAN ET AL: "Designing a Million-Qubit Quantum Computer Using a Resource Performance Simulator", ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS (JETC), vol. 12, no. 4, 28 December 2015 (2015-12-28), 2 Penn Plaza, Suite 701 New York NY 10121-0701 USA, pages 1 - 25, XP055552816, ISSN: 1550-4832, DOI: 10.1145/2830570
- - MARK WHITNEY ET AL: "Automated Generation of Layout and Control for Quantum Circuits", ARXIV.ORG, CORNELL UNIVERSITY LIBRARY, 201 OLIN LIBRARY CORNELL UNIVERSITY ITHACA, NY 14853, 2 April 2007 (2007-04-02), XP080279958, DOI: 10.1145/1242531.1242546
- - TIANHAO ZHANG ET AL: "Design of Reconfigurable Composite Microsystems Based on Hardware/Software Codesign Principles", IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, IEEE, USA, vol. 21, no. 8, 1 August 2002 (2002-08-01), XP011070624, ISSN: 0278-0070