"Enhanced performance in two-dimensional materials based devices through dielectric integration by plasma-enhanced atomic layer deposition“

RWTH Publications (RWTH Aachen)

Abstract

The relentless pursuit of smaller, faster and more efficient electronic devices has driven continuous innovation in transistor technology. As traditional silicon-based transistors approach their fundamental limits, achieving further miniaturization and improved performance presents significant challenges. The push to sustain the progress outlined by Moore’s Law necessitates the exploration of novel materials and architectures. Among the most promising candidates are two-dimensional materials, which, due to their exceptional electrical properties and atomic-scale thickness, offer new opportunities for scaling transistors to unprecedented levels. As transistors channels are scaled down, the thickness of the gate dielectric must also be reduced. Thin, high-quality dielectrics are essential to ensure effective insulation while maintaining transistor performance at smaller dimensions. The goal of this thesis was to develop a plasma-enhanced atomic layer deposition (PEALD) process for depositing high-quality dielectrics on two-dimensional materials, ensuring minimal damage to the materials during deposition. Both field-effect transistors (FETs) and Schottky diodes were fabricated and electrically characterized, with a particular focus on the interaction between the two-dimensional materials and the PEALD dielectrics. This work primarily investigates graphene and MoS₂, which were grown using scalable chemical vapor deposition (CVD) and metal oxide CVD processes. A key objective was to tune the electrical properties of graphene and MoS₂ FETs by controlling the properties of the PEALD dielectrics. The findings demonstrate the potential of PEALD dielectrics for use as gate dielectrics in ultimately scaled metal-oxide semiconductor FETs and as protective layers in graphene-silicon Schottky diodes, showcasing their applicability in next-generation electronic devices. This PhD thesis explores PELAD dielectric layers as gate dielectrics in graphene and MoS2 based FETs and as encapsulation layers in graphene silicon Schottky diodes. In the first part of this research, MoS₂ and graphene were utilized as channel materials in field-effect transistors (FETs) to investigate the impact of dielectric deposition on two-dimensional materials. A novel, scalable, damage-free deposition process using plasma-enhanced atomic layer deposition (PEALD) was developed for the deposition of non-stoichiometric AlOX and standard Al₂O₃ dielectrics on these materials. This process was tested in both back-gated and top-gated FETs. One of the key challenges when working with two-dimensional materials is their inert surface, which makes it difficult to deposit high-quality dielectrics. While several methods have been explored to address this issue, such as using an aluminium seed layer followed by oxidation or thermal deposition techniques, these methods fail to produce the thin, dense layers required for optimal performance. Plasma-enhanced deposition, while effective, often raises concerns about material damage due to the reactivity of the gas species, especially oxygen. To overcome this, the combination of a non-stoichiometric AlOX layer with stoichiometric Al₂O₃ was investigated. This approach not only avoids damage to the two-dimensional materials but also provides a high-k dielectric stack with strong electric field strength, which is crucial for scaling these devices. Furthermore, this method was shown to be scalable to larger substrates, making it a promising approach for industrial applications. The second aspect of the research focused on controlling the doping levels of the two-dimensional materials by engineering the PEALD dielectric layer and the amount of positive fixed charges within it. It was demonstrated that by carefully controlling the thickness of the non-stoichiometric AlOX layer, it is possible to directly modulate the threshold voltage in MoS₂ and the Dirac voltage in graphene. This was achieved in both back-gated configurations, where the AlOX dielectric serves as a passive layer on top of the two-dimensional material channel, and in top-gated configurations, where the AlOX was combined with stoichiometric Al₂O₃, and the dielectric functions as the gate dielectric, actively influencing device operation. The findings highlight the ability to tune key electrical properties of 2D material-based devices by precisely adjusting the dielectric layer, offering new possibilities for optimizing their performance in various electronic applications.

Authors 1

1. Ardeshir Esteki corresponding Aachen

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen