Memory-centric architectures for energy-efficient cryptographic hardware in edge applications

RWTH Publications (RWTH Aachen)

Abstract

The rapid proliferation of digital systems has intensified security challenges and exposed critical vulnerabilities. This evolving threat landscape is further aggravated by the rise of quantum computing, which jeopardizes the security of traditional cryptographic algorithms, particularly those used in asymmetric cryptography. To ensure the security of digital systems in the quantum era, modern security protocols must integrate classical symmetric cryptography and hash functions with emerging post-quantum asymmetric schemes. In parallel, the shift toward resource-constrained edge devices demands highly energy-efficient hardware solutions. Notably, memory operations account for a substantial portion of total energy consumption in digital systems. Therefore, this dissertation focuses on the investigation and development of memory-centric architectures for cryptographic algorithms, optimized for high energy efficiency in edge applications. This dissertation investigates symmetric ciphers, hash functions and lattice-based cryptographic algorithms, while systematically reviewing memory-centric architectures. Key dataflow patterns of these algorithms are extracted to guide the design of energy-efficient memory-centric hardware. Symmetric ciphers and hash functions often incorporate dedicated permutation networks, such as diffusion layers in Substitution Permutation Network (SPN) block ciphers and Linear Feedback Shift Registers (LFSR)-based state updates in stream ciphers and hash functions. Traditional hardware designs rely heavily on homogeneous memory structures, such as shift registers or centralized register files with complex access patterns, which incur significant energy overhead. To address this, this dissertation proposes distributed memory organizations tailored to the unique dataflows of these cryptographic algorithms, which is validated through Application Specific Integrated Circuit (ASIC) implementations of Advanced Encryption Algorithm (AES) and Secure Hash Algorithm-256 (SHA-256). For AES, the accelerator utilizes distributed scratchpad memories to enhance data locality and provide sufficient memory bandwidth to improve hardware utilization. This design achieves a throughput of 1432 Mbps and an energy efficiency of 400 Gbps/W. In the case of SHA-256, the accelerator integrates shift registers and First-In-First-Out (FIFO) buffers to balance write and read costs. This results in a throughput of 31.6 MHash/s and an energy efficiency of 2.7 GHash/J. For post-quantum lattice-based schemes, where polynomial multiplication is the dominant operation, two distinct techniques are introduced. For schemes where Number Theoretic Transform (NTT) is applicable, a Local Horizontal Folding (LHF) algorithm is proposed to map the NTT workload onto a Compute-near-Memory (CNM) architecture with minimal local buffer, exploiting the regularity of butterfly networks. The LHF-NTT approach reduces memory accesses by at least 50% compared to conventional One-Dimensional (1D) NTT implementations while maintaining the same throughput. In the Two-Dimensional (2D) NTT case, the design doubles throughput without increasing memory bandwidth. For schemes where NTT is not suitable, polynomial multiplication exhibits unique data stationarity. To exploit this, a Compute-in-Memory (CIM) architecture is developed to minimize data movement. This methodology is validated on the Binary Ring Learning-with-Error (BRLWE) algorithm, achieving best-in-classperformance with a throughput of 6.92 MOPS and an energy efficiency of 429 MOPS/W. Overall, memory-centric architectures offer a promising path toward achieving high energy efficiency in cryptographic hardware, particularly for edge applications.

Authors 1

1. Shutao Zhang corresponding Aachen

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen