High-speed, low-power comparators utilizing a self-cascode configuration and a dynamically biased preamplifier technique

Abstract

A high-speed, low-power dynamic comparator has been designed in 22 nm FDSOI CMOS technology. A novel technique is presented that utilizes cascading input transistors and a tail capacitor in the current path of the preamplifier, known as the dynamically biased preamplifier technique, to improve the power consumption and the speed of the comparator. For the supply voltage of 0.8 V, post-layout simulations method indicate that the proposed comparator has 17% lower power consumption than the conventional comparator, achieving 0.113 mW, and a 21% decrease in CLK-Q delay, reaching 96 ps for 10 mV input differential voltages. Monte Carlo simulation was conducted, resulting in a small deviation, which confirms the stability of the design.

Authors 2

1. Mohammad Bayazi Aachen Chair of High Frequency Electronics

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Chair of High Frequency Electronics,Aachen,Germany

2. Renato Negra Aachen Chair of High Frequency Electronics

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Chair of High Frequency Electronics,Aachen,Germany