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GUPA: Group-Wise Uniform Pruning Accelerator for Depthwise Separable Convolution

Abstract

Convolutional neural networks (CNNs) face significant deployment challenges on edge devices due to their high memory and computational demands. Depthwise separable convolution (DSC), with its reduced complexity and comparable accuracy, offers a promising solution. In this work, we propose an algorithm-hardware co-design that integrates a group-wise uniform pruning (GUP) strategy specifically tailored for DSC. This approach optimizes depthwise convolution (DWC) by channel pruning and pointwise convolution (PWC) by kernel pruning, with pruned channels in DWC propagating to PWC. Driven by the GUP strategy, we design a dual-engine DSC accelerator that fetches only unpruned weights and activations. Additionally, we optimized the dataflow and timing to minimize latency. The proposed GUP DSC accelerator is implemented in a 22 nm FDSOI technology, operating at a frequency of 1 GHz after signoff, and occupies an area of$0.4 ~\text{mm}^{2}$. With 50 % pruning applied to the MobileNetV1 model, it reduces MAC operations by$\mathbf{7 4. 2 2 \%}$. The accelerator achieves an average energy efficiency of 24 TOPS/W and a throughput of 8365 GOPS.

Authors 5

  1. RWTH Aachen University

    Affiliation as printed

    RWTH Aachen University,Chair of Integrated Digital Systems and Circuit Design,Germany

  2. RWTH Aachen University

    Affiliation as printed

    RWTH Aachen University,Chair of Integrated Digital Systems and Circuit Design,Germany

  3. RWTH Aachen University

    Affiliation as printed

    RWTH Aachen University,Chair of Integrated Digital Systems and Circuit Design,Germany

  4. RWTH Aachen University

    Affiliation as printed

    RWTH Aachen University,Chair of Integrated Digital Systems and Circuit Design,Germany

  5. RWTH Aachen University

    Affiliation as printed

    RWTH Aachen University,Chair of Integrated Digital Systems and Circuit Design,Germany

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