August 08, 2024 article Design of a novel low-latency parameterizable posit adder/subtractor using leading one predictor in FPGA Digital Signal Processing DOI: 10.1016/j.dsp.2024.104718 OpenAlex Authors 0 Author list not loaded yet. Cited by 0 stored of 3 References 1 Search Sort Most cited Newest Oldest Patent citations Title Any typearticle review book-chapter conference-paper preprint dissertation book dataset other Any fieldAgricultural and Biological Sciences Arts and Humanities Biochemistry, Genetics and Molecular Biology Business, Management and Accounting Chemical Engineering Chemistry Computer Science Decision Sciences Dentistry Earth and Planetary Sciences Economics, Econometrics and Finance Energy Engineering Environmental Science Health Professions Immunology and Microbiology Materials Science Mathematics Medicine Neuroscience Nursing Pharmacology, Toxicology and Pharmaceutics Physics and Astronomy Psychology Social Sciences Veterinary Open access CLARINET: A quire-enabled RISC-V-based framework for posit arithmetic empiricism 2022 Journal of Systems Architecture article Computer Science Numerical Methods and Algorithms 18 citations 1 result