16.8 Gbps Fully-Differential Pseudorandom Bit Sequence Generator Exploiting Asynchronous XOR Gate with an FOM of 1.1 pJ/bit on 65-nm CMOS

International Conference on Modern Circuits and Systems Technologies, pp. 1–4

Abstract

This work presents the design, implementation, and characterisation of a low-power fully-differential$\mathbf{2}^{\mathbf{7}}-\mathbf{1}$CMOS pseudorandom bit sequence (PRBS) generator. The high speed is achieved by adapting a half-rate structure with a multiplexer (MUX) and current-mode logic (CML). All the transistors are of low-threshold-voltage$(\mathbf{low}-V_{t})$type to further enhance the data rate. Low-power consumption is obtained by employing an asynchronous XOR gate design alongside careful optimisation of the logic circuits. Clock signals for the XORs are therefore not required. Employing an asynchronous XOR requires a strict symmetrical layout. Measurements shows a data rate of up to 16.8 Gbps, a power consumption of 130 mW from a 1.2-V supply, and a figure-of-merit (FoM) of 1.1 pJ/bit.

Authors 3

1. Yanlu Wang Aachen Chair of High Frequency Electronics

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Chair of High Frequency Electronics,Aachen,Germany,52062

2. Muh‐Dey Wei Aachen Chair of High Frequency Electronics

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Chair of High Frequency Electronics,Aachen,Germany,52062

3. Renato Negra Aachen Chair of High Frequency Electronics

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Chair of High Frequency Electronics,Aachen,Germany,52062