Optimised AES with RISC-V Vector Extensions

Abstract

With the advent of quantum computers, organizations and users should consider the potential impact of quantum threats on their cryptographic systems and be prepared to adopt Post-Quantum Cryptography (PQC) solutions when needed. However, PQC algorithms are often difficult to implement on standard processors and resource-constrained embedded devices, due to complicated mathematical algorithms and large parameters. The goal of this research is to design efficient HW/SW co-design of the PQC algorithm Classic McEliece (CM) using the RISC-V Instruction Set Architecture (ISA). In the first step, the acceleration of the AES algorithm, which is used as part of the key generation in CM, is explored using RISC-V Vector Extensions version 1.0 (RVV1.0). In this paper, we compare the vector-accelerated AES running on Vicuan coprocessor with the scalar AES running on Ibex.

Authors 4

1. Mahnaz Namazi Rizi Aachen

   Leiden University

   Affiliation as printed

   Leiden university,The Netherlands

   Leiden university, The Netherlands

2. Nuša Zidarič Aachen

   Leiden University

   Affiliation as printed

   Leiden university,The Netherlands

   Leiden university, The Netherlands

3. Lejla Batina

   Radboud University Nijmegen

   Affiliation as printed

   Radboud Univerity,The Netherlands

   Radboud Univerity, The Netherlands

4. Nele Mentens Aachen

   Leiden University · KU Leuven

   Affiliation as printed

   Leiden university,The Netherlands

   KU Leuven, Belgium

   Leiden university, The Netherlands