Work-in-Progress: A Generic Non-Intrusive Parallelization Approach for SystemC TLM-2.0-based Virtual Platforms

International Conference on Hardware/Software Codesign and System Synthesis, pp. 42–43

Abstract

The ever-growing complexity of Systems-on-a-Chip (SoCs) requires continuous improvements of development tools such as Virtual Platforms (VPs). VPs are Software (SW)-based functional simulators of SoCs that allow SW development in an early design stage. Any improvement of VP's performance reduces the needed simulation time and thereby accelerates the development process.

Authors 6

1. Nils Bosbach Aachen Institute for Communication Technologies and Embedded Systems

   RWTH Aachen University

   Affiliation as printed

   Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Aachen, NRW, Germany

2. Rebecca Pelke Aachen Institute for Communication Technologies and Embedded Systems

   RWTH Aachen University

   Affiliation as printed

   Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Aachen, NRW, Germany

3. Niko Zurstraßen Aachen Institute for Communication Technologies and Embedded Systems

   RWTH Aachen University

   Affiliation as printed

   Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Aachen, NRW, Germany

4. Lukas Jünger
   Affiliation as printed

   MachineWare GmbH, Aachen, NRW, Germany

5. Jan Henrik Weinstock
   Affiliation as printed

   MachineWare GmbH, Aachen, NRW, Germany

6. Rainer Leupers Aachen Institute for Communication Technologies and Embedded Systems

   RWTH Aachen University

   Affiliation as printed

   Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Aachen, NRW, Germany