AIrchitect: Automating Hardware Architecture and Mapping Optimization

Design, Automation, and Test in Europe, pp. 1–6

Abstract

Design space exploration and optimization is an essential but iterative step in custom accelerator design involving costly search based method to extract maximum performance and energy efficiency. State-of-the-art methods employ data centric approaches to reduce the cost of each iteration but still rely on search algorithms to obtain the optima. This work proposes a learned, constant time optimizer that uses a custom recommendation network called AIrchitect, which is capable of learning the architecture design and mapping space with a 94.3% test accuracy, and predicting optimal configurations, which achieve on an average (GeoMean) 99.9% of the best possible performance on a test dataset with 105GEMM (GEneral Matrix-matrix Multiplication) workloads.

Authors 3

1. Ananda Samajdar

   Georgia Institute of Technology · IBM (United States)

   Affiliation as printed

   Georgia Tech / IBM Research

2. Jan Moritz Joseph Aachen

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen,Aachen,Germany

   RWTH Aachen, Aachen, Germany

3. Tushar Krishna

   Georgia Institute of Technology

   Affiliation as printed

   Georgia Tech,Atlanta,GA,USA

   Georgia Tech, Atlanta, GA, USA