par-gem5: Parallelizing gem5's Atomic Mode
Design, Automation, and Test in Europe, pp. 1–6
Abstract
While the complexity of MPSoCs continues to grow exponentially, their often sequential simulations could only benefit from a linear performance gain since the end of Dennard scaling. As a result, each new generation of MPSoCs requires ever longer simulation times. In this paper, we propose a solution to this problem: par-gem5-the first universally parallelized version of the Full System Simulator (FSS) gem5. It exploits the host system's multi-threading capabilities using a modified conservative, quantum-based Parallel Discrete Event Simulation (PDES). Compared to other parallel approaches, par-gem5 uses relaxed causality constraints, allowing temporal errors to occur. Yet, we show that the system's functionality is retained, and the inaccuracy of simulation statistics, such as simulation time or cache miss rate, can be kept within a single-digit percentage. Furthermore, we extend par-gem5 by a temporal error estimation that assesses the accuracy of a simulation without a sequential reference simulation. Our experiments reached speedups of 24.7× when simulating a 128-core ARM-based MPSoC on a 128-core host system.
Authors 6
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Affiliation as printed
RWTH Aachen University, Institute for Communication Technologies and Embedded Systems
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Affiliation as printed
RWTH Aachen University, Institute for Communication Technologies and Embedded Systems
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Affiliation as printed
RWTH Aachen University, Institute for Communication Technologies and Embedded Systems
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Affiliation as printed
Huawei Technologies
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Affiliation as printed
Huawei Technologies
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Affiliation as printed
RWTH Aachen University, Institute for Communication Technologies and Embedded Systems
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