Dataflow Optimizations in a Sub-uW Data-Driven TCN Accelerator for Continuous ECG Monitoring

IEEE Nordic Circuits and Systems Conference (NorCAS), pp. 1–7

Abstract

Recent biomedical processors increasingly leverage neural networks (NN) for high-quality monitoring of health parameters. Biomedical signals, such as electrocardiogram (ECG) signals, are processed continuously in time domain. Compared to the capabilities of CMOS technology, the constant data rates are very low making leakage the dominant term over dynamic power consumption and, thus, preferring small inference engines. Remarkable energy-efficiency in terms of operation per watt is achieved by throughput-oriented state-of-the-art deep neural network accelerators, which leverage dataflow schemes to minimize the biggest contributor for energy consumption, i.e. data movement. This work specifically considers the aspect of data movement in the context of temporal convolutional network (TCN) inference. In specific, key principles of recent works, i.e. processing element sharing and shift register-based activation memory, are combined with a novel data-driven processing scheme to compile a minimal, highly efficient inference engine, which is capable of solving the demanding CinC'17 dataset. The resulting accelerator is fabricated in a 22 nm FDSOI technology with a footprint of 0.164 mm2and operates down to 0.5 V. In continuous processing the power goes as low as 0.525 µW.

Authors 2

1. Johnson Loh Aachen Chair of Integrated Digital Systems and Circuit Design (IDS)

   RWTH Aachen University

   Affiliation as printed

   Chair of Integrated Digital Systems and Circuit Design, RWTH Aachen University,Aachen,Germany

   Chair of Integrated Digital Systems and Circuit Design, RWTH Aachen University, Aachen, Germany

2. Tobias Gemmeke Aachen Chair of Integrated Digital Systems and Circuit Design (IDS)

   RWTH Aachen University

   Affiliation as printed

   Chair of Integrated Digital Systems and Circuit Design, RWTH Aachen University,Aachen,Germany

   Chair of Integrated Digital Systems and Circuit Design, RWTH Aachen University, Aachen, Germany