A scalable SIMD RISC-V based processor with customized vector extensions for CRYSTALS-kyber

Proceedings - ACM IEEE Design Automation Conference, pp. 733–738

Abstract

This paper uses RISC-V vector extensions to speed up lattice-based operations in architectures based on HW/SW co-design. We analyze the structure of the number-theoretic transform (NTT), inverse NTT (INTT), and coefficient-wise multiplication (CWM) in CRYSTALS-Kyber, a lattice-based key encapsulation mechanism. We propose 12 vector extensions for CRYSTALS-Kyber multiplication and four for finite field operations in combination with two optimizations of the HW/SW interface. This results in a speed-up of 141.7, 168.7, and 245.5 times for NTT, INTT, and CWM, respectively, compared with the baseline implementation, and a speed-up of over four times compared with the state-of-the-art HW/SW co-design using RV32IMC.

Authors 2

1. Nele Mentens Aachen

   Leiden University · KU Leuven

   Affiliation as printed

   Leiden University, The Netherlands and KU Leuven, Belgium

2. Stjepan Picek

   Delft University of Technology

   Affiliation as printed

   Radboud University and Delft University of Technology, The Netherlands