A
Menu
January 01, 2018 conference-paper

Fully parallel RRAM synaptic array for implementing binary neural network with (+1, −1) weights and (+1, 0) neurons

Asia and South Pacific Design Automation Conference (ASP-DAC)

DOI: 10.1109/aspdac.2018.8297384 OpenAlex

Authors 0

  1. Author list not loaded yet.

Cited by 1 stored of 82

1 result

References 0