June 21, 2004 conference-paper A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation Design, Automation, and Test in Europe DOI: 10.1109/date.2004.1268856 OpenAlex Authors 0 Author list not loaded yet. Cited by 1 stored of 481 Search Sort Most cited Newest Oldest Patent citations Title Any typearticle review book-chapter conference-paper preprint dissertation book dataset other Any fieldAgricultural and Biological Sciences Arts and Humanities Biochemistry, Genetics and Molecular Biology Business, Management and Accounting Chemical Engineering Chemistry Computer Science Decision Sciences Dentistry Earth and Planetary Sciences Economics, Econometrics and Finance Energy Engineering Environmental Science Health Professions Immunology and Microbiology Materials Science Mathematics Medicine Neuroscience Nursing Pharmacology, Toxicology and Pharmaceutics Physics and Astronomy Psychology Social Sciences Veterinary Open access Evaluation of Secure Circuit Styles Using Unipolar Logic Gates 2023 IEEE Interregional NEWCAS Conference (NEWCAS) conference-paper Computer Science Physical Unclonable Functions (PUFs) and Hardware Security Open access 2 citations 1 result References 0