A Parallel SystemC Virtual Platform for Neuromorphic Architectures

International Symposium on Quality Electronic Design (ISQED), pp. 1–6

Abstract

With the increasing interest in neuromorphic computing, designers of embedded systems face the challenge of efficiently simulating such platforms to enable architecture design exploration early in the development cycle. Executing artificial neural network applications on neuromorphic systems which are being simulated on virtual platforms (VPs) is an extremely demanding computational task. Nevertheless, it is a vital benchmarking task for comparing different possible architectures. Therefore, exploiting the multicore capabilities of the VP’s host system is essential to achieve faster simulations. Hence, this paper presents a parallel SystemC based VP for RISC-V multicore platforms integrating multiple computing-in-memory neuromorphic accelerators. In this paper, different VP segmentation architectures are explored for the integration of neuromorphic accelerators and are shown their corresponding speedup simulations compared to conventional sequential SystemC execution.

Authors 3

1. Melvin Galicia Aachen Institute for Communication Technologies and Embedded Systems

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Institute for Communication Technologies and Embedded Systems,Aachen,Germany

2. Farhad Merchant Aachen Institute for Communication Technologies and Embedded Systems

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Institute for Communication Technologies and Embedded Systems,Aachen,Germany

3. Rainer Leupers Aachen Institute for Communication Technologies and Embedded Systems

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University,Institute for Communication Technologies and Embedded Systems,Aachen,Germany