MNEMOSENE: Tile Architecture and Simulator for Memristor-based Computation-in-memory
ACM Journal on Emerging Technologies in Computing Systems, vol. 18, pp. 1–24
Abstract
In recent years, we are witnessing a trend toward in-memory computing for future generations of computers that differs from traditional von-Neumann architecture in which there is a clear distinction between computing and memory units. Considering that data movements between the central processing unit (CPU) and memory consume several orders of magnitude more energy compared to simple arithmetic operations in the CPU, in-memory computing will lead to huge energy savings as data no longer needs to be moved around between these units. In an initial step toward this goal, new non-volatile memory technologies, e.g., resistive RAM (ReRAM) and phase-change memory (PCM), are being explored. This has led to a large body of research that mainly focuses on the design of the memory array and its peripheral circuitry. In this article, we mainly focus on the tile architecture (comprising a memory array and peripheral circuitry) in which storage and compute operations are performed in the (analog) memory array and the results are produced in the (digital) periphery. Such an architecture is termed compute-in-memory-periphery (CIM-P). More precisely, we derive an abstract CIM-tile architecture and define its main building blocks. To bridge the gap between higher-level programming languages and the underlying (analog) circuit designs, an instruction-set architecture is defined that is intended to control and, in turn, sequence the operations within this CIM tile to perform higher-level more complex operations. Moreover, we define a procedure to pipeline the CIM-tile operations to further improve the performance. To simulate the tile and perform design space exploration considering different technologies and parameters, we introduce the fully parameterized first-of-its-kind CIM tile simulator and compiler. Furthermore, the compiler is technology-aware when scheduling the CIM-tile instructions. Finally, using the simulator, we perform several preliminary design space explorations regarding the three competing technologies, ReRAM, PCM, and STT-MRAM concerning CIM-tile parameters, e.g., the number of ADCs. Additionally, we investigate the effect of pipelining in relation to the clock speeds of the digital periphery assuming the three technologies. In the end, we demonstrate that our simulator is also capable of reporting energy consumption for each building block within the CIM tile after the execution of in-memory kernels considering the data-dependency on the energy consumption of the memory array. All the source codes are publicly available.
Authors 9
-
Delft University of Technology
Affiliation as printed
Delft University of Technology, Mekelweg, The Netherlands
-
Delft University of Technology
Affiliation as printed
Delft University of Technology, Mekelweg, The Netherlands
-
Christopher Bengel Aachen
Affiliation as printed
RWTH Aachen University, Germany
-
Dirk J. Wouters Aachen
Affiliation as printed
RWTH Aachen University, Germany
-
Affiliation as printed
Peter-Grünberg-Institut, Germany
-
Affiliation as printed
IBM Research–Zurich, Switzerland
-
Affiliation as printed
IBM Research–Zurich, Switzerland
-
Delft University of Technology
Affiliation as printed
Delft University of Technology, Mekelweg, The Netherlands
-
Delft University of Technology
Affiliation as printed
Delft University of Technology, Mekelweg, The Netherlands
Cited by 22 stored of 23
Cited by patents worldwide 2 (Lens.org)
-
Setting method of in-memory computing simulatorUS12124360B2 2024-10-22 Active
-
SETTING METHOD OF IN-MEMORY COMPUTING SIMULATORUS20240078170A1 2024-03-07 Active