Software Compilation and Optimization Techniques for Heterogeneous Multi‐core Platforms

Abstract

This chapter addresses the challenges associated with compilation and optimization techniques for heterogeneous multi-core computing systems in the embedded industry. The dataflow modeling (especially process networks) is discussed. A retargetable source-to-source compiler has been developed to provide the key capabilities that facilitate the construction of compiler infrastructures for real-world, complex multi-core architectures. Their details and some optimization techniques for software distribution are explained. The most notable process is the software distribution, which accounts for mapping computation (processes) onto the heterogeneous cores of the platform and communication (channels) to communication resources (e.g. communication APIs, memories and interconnect). Given the requirements imposed by the process network programming model, MAPS relies on the analysis of traces to determine static and hybrid mappings, as discussed.

Authors 3

1. Weihua Sheng

   Huawei Technologies (China)

   Affiliation as printed

   Hong Kong Research Center, Huawei, Hong Kong, China

2. Jerónimo Castrillón

   Technische Universität Dresden

   Affiliation as printed

   Chair for Compiler Construction, TU Dresden, Germany

3. Rainer Leupers Aachen Institute for Communication Technologies and Embedded Systems

   RWTH Aachen University

   Affiliation as printed

   Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Germany