ASIP‐Based Multi‐Processor Systems for an Efficient Implementation of CNNs

Abstract

Convolutional neural networks (CNNs) that are used for the analysis of video signals are very compute-intensive. Tasks such as scene segmentation for autonomous driving need CNNs with a greater number of large-sized layers. This chapter begins with the study of suitable application-specific instruction set processor (ASIP) architectures for single-core solutions, subsequently extending the approach to an multi-processor system-on-chip (MPSoC) solution. It introduces related works from the area of hardware accelerators for deep learning and NoC-based multi-core systems. The chapter introduces the relevant NoC components used for the MPSoC and gives an overview of the multi-core system. It investigates the scalability of the core and identifies limiting factors based on fully synthesized circuits in a 28 nm TSMC technology. Several parameter studies of the MPSoC are also executed.

Authors 3

1. Andreas Bytyn Aachen Institute for Communication Technologies and Embedded Systems

   RWTH Aachen University

   Affiliation as printed

   Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Germany

2. René Ahlsdorf Aachen Institute for Communication Technologies and Embedded Systems

   RWTH Aachen University

   Affiliation as printed

   Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Germany

3. Gerd Ascheid Aachen Institute for Communication Technologies and Embedded Systems

   RWTH Aachen University

   Affiliation as printed

   Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Germany