System-level Performance Analysis of High-Data-Rate Frequency-to-Amplitude Converter based CPFSK Transceiver at 60 GHz

IEEE Radio and Wireless Symposium (RWS), vol. 113, pp. 57–59

Abstract

This work presents a system-level analysis of a low-power-consumption continuous-phase frequency-shift-keying (CPFSK) transceiver with a frequency-to-amplitude converter (FAC). The FAC is based on an LC tank and its quality factor (Q) is thoroughly investigated in this paper. The system model is built to evaluate the impacts of Q, phase noise of DCO, noise figure of LNA, transmission distance, and data rate. Based on the study, a CPFSK TRX is able to achieve a data rate of 20 Gbps with a BER of 10-4for a transmission distance of 0.4 m. Because of the FAC, an ultralow-power CPFSK receiver is realisable and it reaches a figure of merit (FOM) of 3 pJ/bit according to the model. It provides a guideline for the design of individual blocks to meet a set of system-level specifications. All these models are developed in VerilogA.

Authors 3

1. Yanlu Wang Aachen Chair of High Frequency Electronics

   RWTH Aachen University

   Affiliation as printed

   Chair of High Frequency Electronics, RWTH Aachen University, Aachen, Germany

2. Muh‐Dey Wei Aachen Chair of High Frequency Electronics

   RWTH Aachen University

   Affiliation as printed

   Chair of High Frequency Electronics, RWTH Aachen University, Aachen, Germany

3. Renato Negra Aachen Chair of High Frequency Electronics

   RWTH Aachen University

   Affiliation as printed

   Chair of High Frequency Electronics, RWTH Aachen University, Aachen, Germany