ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework

International Conference on VLSI Design and International Conference on Embedded Systems (VLSID), vol. 27, pp. 270–275

Abstract

With the growing demands of consumer electronic products, the computational requirements are increasing exponentially. Due to the applications' computational needs, the computer architects are trying to pack as many cores as possible on a single die for accelerated execution of the application program codes. In a multiprocessor system-on-chip (MPSoC), striking a balance among the number of cores, memory subsystems, and network-on-chip parameters is essential to attain the desired performance. In this paper, we present ANDROMEDA, a RISC-V based framework that allows us to explore the different configurations of an MPSoC and observe the performance penalties and gains. We emulate the various configurations of MPSoC on the Synopsys HAPS-80D Dual FPGA platform. Using STREAM, matrix multiply, and N-body simulations as benchmarks, we demonstrate our framework's efficacy in quickly identifying the right parameters for efficient execution of these benchmarks.

Authors 6

1. Farhad Merchant Aachen Institute for Communication Technologies and Embedded Systems

   RWTH Aachen University

   Affiliation as printed

   Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Germany

   [Institute for Communication Technologies and Embedded Systems RWTH Aachen University, Germany]

2. Dominik Šišejković Aachen Institute for Communication Technologies and Embedded Systems

   RWTH Aachen University

   Affiliation as printed

   Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Germany

   [Institute for Communication Technologies and Embedded Systems RWTH Aachen University, Germany]

3. Lennart M. Reimann Aachen Institute for Communication Technologies and Embedded Systems

   RWTH Aachen University

   Affiliation as printed

   Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Germany

   [Institute for Communication Technologies and Embedded Systems RWTH Aachen University, Germany]

4. Kirthihan Yasotharan Aachen Institute for Communication Technologies and Embedded Systems

   RWTH Aachen University

   Affiliation as printed

   Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Germany

   [Institute for Communication Technologies and Embedded Systems RWTH Aachen University, Germany]

5. Thomas Grass Aachen Institute for Communication Technologies and Embedded Systems

   RWTH Aachen University

   Affiliation as printed

   Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Germany

   [Institute for Communication Technologies and Embedded Systems RWTH Aachen University, Germany]

6. Rainer Leupers Aachen Institute for Communication Technologies and Embedded Systems

   RWTH Aachen University

   Affiliation as printed

   Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Germany

   RWTH Aachen University