Fireiron

Abstract

High GPU performance can only be achieved if a kernel efficiently uses the multi-layered compute and memory hierarchies. For example, accelerators such as NVIDIA ?s Tensor Cores require specific mappings of threads to data that must be considered in data movements to and from registers. Current compilers struggle to match the performance of vendor libraries like cu BLAS , which are developed by experts in assembly. This manual low-level coding is time-consuming and complicates to unlock the full GPU potential, preventing experimentation to achieve even higher performance. In this paper we introduce Fireiron, a scheduling language aimed at performance experts. Fireiron provides high-level abstractions for expressing GPU optimizations that are unavailable to compilers today and which so far must be written in assembly. Our innovation is that both computations and data movements are first class concepts that can be separately mapped to threads, as required for the efficient use of specialized hardware like Tensor Cores. We evaluate Fireiron on three GPU architectures against expert-written advanced matrix multiplications. First, we show that Fireiron schedules are able to express the strategies of these implementations requiring about 6× less lines of code. Second, we show that the code generated by Fireiron schedules outperforms the fastest implementations (provided by cu BLAS ) by more than 2×.

Authors 5

1. Bastian Hagedorn

   University of Münster

   Affiliation as printed

   University of Münster, Münster, Germany

2. Archibald Samuel Elliott
   Affiliation as printed

   lowRISC, Cambridge, United Kingdom

3. Henrik Barthels Aachen

   RWTH Aachen University

   Affiliation as printed

   RWTH Aachen University, Aachen, Germany

4. Rastislav Bodík

   University of Washington

   Affiliation as printed

   University of Washington, Seattle, WA, USA

5. Vinod Grover

   Nvidia (United States)

   Affiliation as printed

   NVIDIA Corporation, Redmond, WA, USA