December 14, 2019 article General memory efficient packet matching FPGA architecture for future high-speed networks Microprocessors and Microsystems DOI: 10.1016/j.micpro.2019.102950 OpenAlex Authors 0 Author list not loaded yet. Cited by 2 stored of 16 Search Sort Most cited Newest Oldest Patent citations Title Any typearticle review book-chapter conference-paper preprint dissertation book dataset other Any fieldAgricultural and Biological Sciences Arts and Humanities Biochemistry, Genetics and Molecular Biology Business, Management and Accounting Chemical Engineering Chemistry Computer Science Decision Sciences Dentistry Earth and Planetary Sciences Economics, Econometrics and Finance Energy Engineering Environmental Science Health Professions Immunology and Microbiology Materials Science Mathematics Medicine Neuroscience Nursing Pharmacology, Toxicology and Pharmaceutics Physics and Astronomy Psychology Social Sciences Veterinary Open access Designing Hardware-Friendly Hash Functions for Network Security Using Cartesian Genetic Programming 2025 Lecture notes in computer science conference-paper Computer Science Network Packet Processing and Optimization Open access 0 citations A Systematic Exploration of Evolutionary Computation for the Design of Hardware-oriented Non-cryptographic Hash Functions 2024 Genetic and Evolutionary Computation Conference (GECCO) conference-paper Computer Science Evolutionary Algorithms and Applications Open access 2 citations 2 results References 0