September 01, 2015 conference-paper A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology IEEE Custom Integrated Circuits Conference (CICC) DOI: 10.1109/cicc.2015.7338432 OpenAlex Authors 0 Author list not loaded yet. Cited by 1 stored of 13 Search Sort Most cited Newest Oldest Patent citations Title Any typearticle review book-chapter conference-paper preprint dissertation book dataset other Any fieldAgricultural and Biological Sciences Arts and Humanities Biochemistry, Genetics and Molecular Biology Business, Management and Accounting Chemical Engineering Chemistry Computer Science Decision Sciences Dentistry Earth and Planetary Sciences Economics, Econometrics and Finance Energy Engineering Environmental Science Health Professions Immunology and Microbiology Materials Science Mathematics Medicine Neuroscience Nursing Pharmacology, Toxicology and Pharmaceutics Physics and Astronomy Psychology Social Sciences Veterinary Open access A Fast and Accurate True Event-driven Phase Locked Loop Model 2020 IEEE International Conference on Electronics, Circuits and Systems (ICECS) conference-paper Engineering Advancements in PLL and VCO Technologies 6 citations 1 result References 0